View IC41LV16100A-50T_6438202.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 1 dr030-0a 09/28/2001 document title 1m x 16 bit dynamic ram with edo page mode revision history revision no history draft date remark 0a initial draft september 28,2001
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 2 integrated circuit solution inc. dr030-0a 09/28/2001 icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. features ? extended data-out (edo) page mode access cycle ? ttl compatible inputs and outputs; tristate i/o ? refresh interval: 1,024 cycles /16 ms ? refresh mode : ras -only, cas -before- ras (cbr), and hidden ? jedec standard pinout ? single power supply: 5v 10% (ic41c16100a(s)) 3.3v 10% (ic41lv16100a(s)) ? byte write and byte read operation via two cas ? self refresh 1024 cycles for s version description the icsi ic41c16100a(s) and ic41lv16100a(s) are 1,048, 576 x 16-bit high-performance cmos dynamic random access memories. these devices offer an accelerated cycle access called edo page mode. edo page mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. the byte write control, of upper and lower byte, makes the 16100 series ideal for use in 16-, 32-bit wide data bus systems. these features make the ic41c16100a(s) and ic41lv16100a (s) ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. the ic41c16100a(s) and ic41lv16100a(s) are packaged in a 42-pin 400mil soj and 400mil 50- (44-) pin tsop-2. 1m x 16 (16-mbit) dynamic ram with edo page mode key timing parameters parameter -50 -60 unit max. ras access time (t rac )5060ns max. cas access time (t cac )1315ns max. column address access time (t aa )2530ns min. edo page mode cycle time (t pc )2025ns min. read/write cycle time (t rc ) 84 104 ns 42-pin soj pin configurations 50(44)-pin tsop-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 vcc i/o0 i/o1 i/o2 i/o3 vcc i/o4 i/o5 i/o6 i/o7 nc nc we ras nc nc a0 a1 a2 a3 vcc gnd i/o15 i/o14 i/o13 i/o12 gnd i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a9 a8 a7 a6 a5 a4 gnd pin descriptions a0-a9 address inputs i/o0-15 data inputs/outputs we write enable oe output enable ras row address strobe ucas upper column address strobe lcas lower column address strobe vcc power gnd ground nc no connection 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 vcc i/o0 i/o1 i/o2 i/o3 vcc i/o4 i/o5 i/o6 i/o7 nc nc nc we ras nc nc a0 a1 a2 a3 vcc gnd i/o15 i/o14 i/o13 i/o12 gnd i/o11 i/o10 i/o9 i/o8 nc nc lcas ucas oe a9 a8 a7 a6 a5 a4 gnd
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 3 dr030-0a 09/28/2001 functional block diagram oe we lcas ucas cas we oe data i/o bus column decoders sense amplifiers memory array 1,048,576 x 16 row decoder data i/o buffers cas clock generator we control logics oe control logic i/o0-i/o15 ras ras a0-a9 ras clock generator refresh counter address buffers
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 4 integrated circuit solution inc. dr030-0a 09/28/2001 truth table function ras ras ras ras ras lcas lcas lcas lcas lcas ucas ucas ucas ucas ucas we we we we we oe oe oe oe oe address t r /t c i/o standby h h h x x x high-z read: word l l l h l row/col d out read: lower byte l l h h l row/col lower byte, d out upper byte, high-z read: upper byte l h l h l row/col lower byte, high-z upper byte, d out write: word (early write) l l l l x row/col d in write: lower byte (early write) l l h l x row/col lower byte, d in upper byte, high-z write: upper byte (early write) l h l l x row/col lower byte, high-z upper byte, d in read-write (1,2) lllh ll h row/col d out , d in edo page-mode read (2) 1st cycle: l h lh l h l row/col d out 2nd cycle: l h lh l h l na/col d out any cycle: l l hl h h l na/na d out edo page-mode write (1) 1st cycle: l h lh l l x row/col d in 2nd cycle: l h lh l l x na/col d in edo page-mode (1,2) 1st cycle: l h lh lh ll h row/col d out , d in read-write 2nd cycle: l h lh lh ll h na/col d out , d in hidden refresh read (2) l h l l l h l row/col d out write (1,3) l h l l l l x row/col d in ras -only refresh l h h x x row/na high-z cbr refresh (4) h l l l x x x high-z notes: 1. these write cycles may also be byte write cycles (either lcas or ucas active). 2. these read cycles may also be byte read cycles (either lcas or ucas active). 3. early write only. 4. at least one of the two cas signals must be active ( lcas or ucas ).
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 5 dr030-0a 09/28/2001 functional description the ic41c16100a(s) and ic41lv16100a(s) is a cmos dram optimized for high-speed bandwidth, low power applications. during read or write cycles, each bit is uniquely addressed through the 16 address bits. these are entered ten bits (a0-a9) at a time. the row address is latched by the row address strobe ( ras ). the column address is latched by the column address strobe ( cas ). ras is used to latch the first ten bits and cas is used the latter ten bits. the ic41c16100a(s) and ic41lv16100a(s) has two cas controls, lcas and ucas . the lcas and ucas inputs internally generates a cas signal functioning in an iden- tical manner to the single cas input on the other 1m x 16 drams. the key difference is that each cas controls its corresponding i/o tristate logic (in conjunction with oe and we and ras ). lcas controls i/o0 through i/o7 and ucas controls i/o8 through i/o15. the ic41c16100a(s) and ic41lv16100a(s) cas func- tion is determined by the first cas ( lcas or ucas ) transitioning low and the last transitioning back high. the two cas controls give the ic41c16100a(s) and is41lv16100a(s) both byte read and byte write cycle capabilities. memory cycle a memory cycle is initiated by bring ras low and it is terminated by returning both ras and cas high. to ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. a new cycle must not be initiated until the minimum precharge time t rp , t cp has elapsed. read cycle a read cycle is initiated by the falling edge of cas or oe , whichever occurs last, while holding we high. the column address must be held for a minimum time specified by t ar . data out becomes valid only when t rac , t aa , t cac and t oea are all satisfied. as a result, the access time is dependent on the timing relationships between these parameters. write cycle a write cycle is initiated by the falling edge of cas and we , whichever occurs last. the input data must be valid at or before the falling edge of cas or we , whichever occurs first. refresh cycle to retain data, 1,024 refresh cycles are required in each 16 ms period. there are two ways to refresh the memory. 1. by clocking each of the 1,024 row addresses (a0 through a9) with ras at least once every 16 ms. any read, write, read-modify-write or ras -only cycle re- freshes the addressed row. 2. using a cas -before- ras refresh cycle. cas -before- ras refresh is activated by the falling edge of ras , while holding cas low. in cas -before- ras refresh cycle, an internal 10-bit counter provides the row ad- dresses and the external address inputs are ignored. cas -before- ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. self refresh cycle the self refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms. i.e., 125 s per row when using distributed cbr refreshes. the feature also allows the user the choice of a fully static, low power data retention mode. the optional self refresh feature is initiated by performing a cbr refresh cycle and holding ras low for the specified t rass . the self refresh mode is terminated by driving ras high for a minimum time of t rps . this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras low-to-high transition. if the dram controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram controller utilizes a ras -only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the re- sumption of normal operation. extended data out page mode edo page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate. in edo page mode read cycle, the data-out is held to the next cas cycle?s falling edge, instead of the rising edge. for this reason, the valid data output time in edo page mode is extended compared with the fast page mode. in the fast page mode, the valid data output time becomes shorter as the cas cycle time becomes shorter. therefore, in edo page mode, the timing margin in read cycle is larger than that of the fast page mode even if the cas cycle time becomes shorter. in edo page mode, due to the extended data function, the cas cycle time can be shorter than in the fast page mode if the timing margin is the same. the edo page mode allows both read and write opera- tions during one ras cycle, but the performance is equivalent to that of the fast page mode in that case. power-on after application of the v cc supply, an initial pause of 200 s is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a ras signal). during power-on, it is recommended that ras track with v cc or be held at a valid v ih to avoid current surges.
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 6 integrated circuit solution inc. dr030-0a 09/28/2001 absolute maximum ratings (1) symbol parameters rating unit v t voltage on any pin relative to gnd 5v ?1.0 to +7.0 v 3.3v ?0.5 to +4.6 v cc supply voltage 5v ?1.0 to +7.0 v 3.3v ?0.5 to +4.6 i out output current 50 ma p d power dissipation 1 w t a commercial operation temperature 0 to +70 c t stg storage temperature ?55 to +125 c note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (voltages are referenced to gnd.) symbol parameter min. typ. max. unit v cc supply voltage 5v 4.5 5.0 5.5 v 3.3v 3.0 3.3 3.6 v ih input high voltage 5v 2.4 ? v cc + 1.0 v 3.3v 2.0 ? v cc + 0.3 v il input low voltage 5v ?1.0 ? 0.8 v 3.3v ?0.3 ? 0.8 t a commercial ambient temperature 0 ? 70 c capacitance (1,2) symbol parameter max. unit c in 1 input capacitance: a0-a9 5 pf c in 2 input capacitance: ras , ucas , lcas , we , oe 7pf c io data input/output capacitance: i/o0-i/o15 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz.
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 7 dr030-0a 09/28/2001 electrical characteristics (1) (recommended operating conditions unless otherwise noted.) symbol parameter test condition speed min. max. unit i il input leakage current any input 0v v in vcc ?5 5 a other inputs not under test = 0v i io output leakage current output is disabled (hi-z) ?5 5 a 0v v out vcc v oh output high voltage level i oh = ?5.0 ma (5v) 2.4 ? v i oh = ?2.0 ma (3.3v) v ol output low voltage level i ol = 4.2 ma (5v) ? 0.4 v i ol = 2.0 ma (3.3v) i cc 1 standby current: ttl ras , lcas , ucas v ih commerical 5v ? 2 ma 3.3v ? 2 i cc 2 standby current: cmos ras , lcas , ucas v cc ? 0.2v 5v ? 1 ma 3.3v ? 0.5 i cc 3 operating current: ras , lcas , ucas , -50 ? 160 ma random read/write (2,3,4) address cycling, t rc = t rc (min.) -60 ? 145 average power supply current i cc 4 operating current: ras = v il , lcas , ucas , -50 ? 90 ma edo page mode (2,3,4) cycling t pc = t pc (min.) -60 ? 80 average power supply current i cc 5 refresh current: ras cycling, lcas , ucas v ih -50 ? 160 ma ras -only (2,3) t rc = t rc (min.) -60 ? 145 average power supply current i cc 6 refresh current: ras , lcas , ucas cycling -50 ? 160 ma cbr (2,3,5) t rc = t rc (min.) -60 ? 145 average power supply current i ccs self refresh current self refresh mode 5v ? 500 a 3.3v ? 300 a notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. dependent on cycle rates. 3. specified values are obtained with minimum cycle time and the output open. 4. column-address is changed once each edo page cycle. 5. enables on-chip refresh and address counters.
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 8 integrated circuit solution inc. dr030-0a 09/28/2001 ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 -60 symbol parameter min. max. min. max. units t rc random read or write cycle time 84 ? 104 ? ns t rac access time from ras (6, 7) ?50?60 ns t cac access time from cas (6, 8, 15) ?13?15 ns t aa access time from column-address (6) ?25?30 ns t ras ras pulse width 50 10k 60 10k ns t rp ras precharge time 30 ? 40 ? ns t cas cas pulse width (26) 810k1010kns t cp cas precharge time (9, 25) 10 ? 10 ? ns t csh cas hold time (21) 38 ? 40 ? ns t rcd ras to cas delay time (10, 20) 12 37 14 45 ns t asr row-address setup time 0 ? 0 ? ns t rah row-address hold time 8 ? 10 ? ns t asc column-address setup time (20) 0?0?ns t cah column-address hold time (20) 8?10?ns t rad ras to column-address delay time (11) 10 25 12 30 ns t ral column-address to ras lead time 25 ? 30 ? ns t rsh ras hold time (27) 8?10?ns t rhcp ras hold time from cas precharge 35 ? 37 ? ns t clz cas to output in low-z (15, 29) 0?0?ns t crp cas to ras precharge time (21) 5?5?ns t od output disable time (19, 28, 29) 012015ns t oe output enable time (15, 16) ?12?15 ns t oed output enable data delay (write) 20 ? 20 ? ns t oehc oe high hold time from cas high 5 ? 5 ? ns t oep oe high pulse width 10 ? 10 ? ns t rcs read command setup time (17, 20) 5?5?ns t rrh read command hold time 10 ? 10 ? ns (referenced to ras ) (12) t rch read command hold time 0 ? 0 ? ns (referenced to cas ) (12, 17, 21) t wch write command hold time (17, 27) 8?10?ns t wp write command pulse width (17) 8?10?ns t wpz we pulse widths to disable outputs 10 ? 10 ? ns t rwl write command to ras lead time (17) 13 ? 15 ? ns t cwl write command to cas lead time (17, 21) 8?10?ns t wcs write command setup time (14, 17, 20) 0?0?ns
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 9 dr030-0a 09/28/2001 ac characteristics (continued) (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 -60 symbol parameter min. max. min. max. units t oeh oe hold time from we during 8 ? 10 ? ns read-modify-write cycle (18) t ds data-in setup time (15, 22) 0?0?ns t dh data-in hold time (15, 22) 8?10?ns t rwc read-modify-write cycle time 108 ? 133 ? ns t rwd ras to we delay time during 64 ? 77 ? ns read-modify-write cycle (14) t cwd cas to we delay time (14, 20) 26 ? 32 ? ns t awd column-address to we delay time (14) 39 ? 47 ? ns t pc edo page mode read or write 20 ? 25 ? ns cycle time (24) t rasp ras pulse width in edo page mode 50 100k 60 100k ns t cpa access time from cas precharge (15) ?30?35ns t prwc edo page mode read-write 56 ? 68 ? ns cycle time (24) t coh data output hold after cas low 5 ? 5 ? ns t off output buffer turn-off delay from 0 12 0 15 ns cas or ras (13,15,19, 29) t whz output disable delay from we 310310ns t csr cas setup time (cbr refresh) (30, 20) 5?5?ns t chr cas hold time (cbr refresh) (30, 21) 8?10?ns t rpc ras to cas precharge time 5 ? 5 ? ns t ord oe setup time prior to ras during 0 ? 0 ? ns hidden refresh cycle t ref auto refresh period (1,024 cycles) ? 16 ? 16 ms t t transition time (rise or fall) (2, 3) 150150ns ac test conditions output load: two ttl loads and 50 pf (vcc = 5.0v 10%) one ttl load and 50 pf (vcc = 3.3v 10%) input timing reference levels: v ih = 2.4v, v il = 0.8v (vcc = 5.0v 10%); v ih = 2.0v, v il = 0.8v (vcc = 3.3v 10%) output timing reference levels: v oh = 2.0v, v ol = 0.8v (vcc = 5v 10%, 3.3v 10%)
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 10 integrated circuit solution inc. dr030-0a 09/28/2001 notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycle ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times, are measured between v ih and v il (or between v il and v ih ) and assume to be 1 ns for all inputs. 3. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. if cas and ras = v ih , data output is high-z. 5. if cas = v il , data output may contain data from the last valid read cycle. 6. measured with a load equivalent to one ttl gate and 50 pf. 7. assumes that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 8. assumes that t rcd > t rcd (max). 9. if cas is low at the falling edge of ras , data out will be maintained from the previous cycle. to initiate a new cycle and clear the data output buffer, cas and ras must be pulsed for t cp . 10. operation with the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, access time is controlled exclusively by t cac . 11. operation within the t rad (max) limit ensures that t rcd (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t aa . 12. either t rch or t rrh must be satisfied for a read cycle. 13. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 14. t wcs , t rwd , t awd and t cwd are restrictive operating parameters in late write and read-modify-write cycle only. if t wcs > t wcs (min), the cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. if t rwd > t rwd (min), t awd > t awd (min) and t cwd > t cwd (min), the cycle is a read-write cycle and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write ( oe -controlled) cycle. 15. output parameter (i/o) is referenced to corresponding cas input, i/o0-i/o7 by lcas and i/o8-i/o15 by ucas . 16. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open. if oe is tied permanently low, a late write or read-modify-write is not possible. 17. write command is defined as we going low. 18. late write and read-modify-write cycles must have both t od and t oeh met ( oe high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the i/os will provide the previously written data if cas remains low and oe is taken back to low after t oeh is met. 19. the i/os are in open during read cycles once t od or t off occur. 20. the first cas edge to transition low. 21. the last cas edge to transition high. 22. these parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read- modify-write cycles. 23. last falling cas edge to first rising cas edge. 24. last rising cas edge to next cycle?s last rising cas edge. 25. last rising cas edge to first falling cas edge. 26. each cas must meet minimum pulse width. 27. last cas to go low. 28. i/os controlled, regardless ucas and lcas . 29. the 3 ns minimum is a parameter guaranteed by design. 30. enables on-chip refresh and address counters.
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 11 dr030-0a 09/28/2001 read cycle note: 1. t off is referenced from rising edge of ras or cas , whichever occurs last. t ras t rc t rp t cah t asc t rad t ral oe i/o we address ucas/lcas ras row column row open open valid data t csh t cas t rsh t crp t rcd t rah t asr t rrh t rch t rcs t aa t cac t off (1) t rac t clz t oes t oe t od undefined don?t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 12 integrated circuit solution inc. dr030-0a 09/28/2001 early write cycle ( oe = don't care) t ras t rc t rp t cah t asc t rad t ral i/o we address ucas/lcas ras row column row t csh t cas t rsh t crp t rcd t rah t asr t cwl t wcr t wch t rwl t wp t wcs t dh t ds valid data don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 13 dr030-0a 09/28/2001 read write cycle (late write and read-modify-write cycles) t ras t rwc t rp t cah t asc t rad t ral we oe address ucas/lcas ras row column row t csh t cas t rsh t crp t rcd t rah t asr t rwd t cwl t cwd t rwl t awd t wp t rcs t cac t clz t ds t dh t oeh t od t oe t rac t aa i/o open open valid d out valid d in undefined don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 14 integrated circuit solution inc. dr030-0a 09/28/2001 edo-page-mode read cycle note: 1. t pc can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas . both measurements must meet the t pc specifications. t rasp t rp address ucas/lcas ras row row t cas t crp t rcd t csh t cp t cas t cah t cas t ral t rsh t cp t cp t pc (1) t asr t rah t rad column column t cah t cah column t asc t asc oe i/o we open open valid data t aa t aa t cpa t cac t cac t rac t coh t clz t oep t oe t od t oe t oehc valid data t rch t rrh t aa t cpa t cac t off t clz valid data t od t asc t rcs undefined don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 15 dr030-0a 09/28/2001 edo-page-mode early-write cycle t rasp t rp address ucas/lcas ras row row t cas t crp t rcd t csh t cp t cas t cah t cas t ral t rsh t cp t cp t pc t asr t rah t rad column column t cah t cah column t asc t asc oe i/o we valid data t asc t wcs t wch t cwl t wp t rhcp t wcs t wch t cwl t wp t dh t ds t wcs t wch t cwl t wp valid data t ds t dh valid data t ds t rwl t dh don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 16 integrated circuit solution inc. dr030-0a 09/28/2001 edo-page-mode read-write cycle (late write and read-modify write cycles) note: 1. t pc is for late write only. t pc can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas . both measurements must meet the t pc specifications. t rasp t rp address ucas/lcas ras row row t crp t rcd t csh t cp t cah t cas t ral t rsh t cp t cp t rah t rad t asr column column t cah t cah column t asc t asc t cas t cas oe i/o we t asc t rwd t rcs t cwl t wp t awd t cwd t dh t ds t cac t clz t awd t cwd t cwl t wp t awd t cwd t cwl t rwl t wp open open d in d out t oe t oe t oe t od t oeh t od t od t dh t ds t cpa t aa t cac t clz d in d out t dh t ds t cac t clz d in d out t cpa t aa t rac t aa t pc / t prwc (1) undefined don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 17 dr030-0a 09/28/2001 edo-page-mode read-early-write cycle (psuedo read-modify write) t rasp t rp address ucas/lcas ras row row t crp t rcd t pc t csh t cp t cah t cas t ral t rsh t cp t cp t rah t rad t asr column (a) column (n) t cah t cah column (b) t asc t asc t cas t cas oe i/o we t asc t cac t rch t dh open open valid data (a) t oe t wcs t cac t coh d in t cpa t wch t rac t aa t pc valid data (b) t whz t ds t rcs t aa don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 18 integrated circuit solution inc. dr030-0a 09/28/2001 ac waveforms read cycle (with we -controlled disable) ras ras ras ras ras -only refresh cycle ( oe , we = don't care) t cah t asc t asc t rad oe i/o we address ucas/lcas ras row column open open valid data t csh t cas t crp t rcd t cp t rah t asr t rch t rcs t rcs t aa t cac t whz t rac t clz t clz t oe t od column t ras t rc t rp i/o address ucas/lcas ras row row open t crp t rah t asr t rpc undefined don ? t care don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 19 dr030-0a 09/28/2001 hidden refresh cycle (1) ( we = high; oe = low) cbr refresh cycle (addresses; we , oe = don't care) notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high. 2. t off is referenced from rising edge of ras or cas , whichever occurs last. t ras t ras t rp t rp i/o ucas/lcas ras open t cp t rpc t csr t chr t rpc t csr t chr t ras t ras t rp ucas/lcas ras t crp t rcd t rsh t chr t asc t rad address row column t rah t asr t ral t cah i/o open open valid data t aa t cac t rac t clz t off (2) oe t oe t ord t od undefined don ? t care
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as 20 integrated circuit solution inc. dr030-0a 09/28/2001 self refresh cycle (addresses : we and oe = don't care) t rass t rp t rps dq ucas/lcas ras open t cp v ih v il v ih v il v oh v ol t rpc t csr t chd t rpc t cp don ? t care timing parameters -50 -60 symbol min. max. min. max. units t chd 8? 10? ns t cp 10 ? 10 ? ns t csr 5? 5? ns t rass 100 ? 100 ? s t rp 30 ? 40 ? ns t rps 84 ? 104 ? ns t rpc 5? 5? ns ordering information: 5v commercial range: 0c to 70c speed (ns) order part no. package 50 ic41c16100a-50k 400mil soj ic41c16100a-50t 400mil tsop-2 60 ic41c16100a-60k 400mil soj ic41c16100a-60t 400mil tsop-2 ordering information: 5v commercial range: 0c to 70c speed (ns) order part no. package 50 ic41c16100as-50k 400mil soj ic41c16100as-50t 400mil tsop-2 60 ic41c16100as-60k 400mil soj ic41c16100as-60t 400mil tsop-2
ic41c16100a/ic41c16100as ic41lv16100a/ic41lv16100as integrated circuit solution inc. 21 dr030-0a 09/28/2001 integrated circuit solution inc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw ordering information: 3.3v commercial range: 0c to 70c speed (ns) order part no. package 50 ic41lv16100a-50k 400mil soj IC41LV16100A-50T 400mil tsop-2 60 ic41lv16100a-60k 400mil soj ic41lv16100a-60t 400mil tsop-2 ordering information: 3.3v commercial range: 0c to 70c speed (ns) order part no. package 50 ic41lv16100as-50k 400mil soj ic41lv16100as-50t 400mil tsop-2 60 ic41lv16100as-60k 400mil soj ic41lv16100as-60t 400mil tsop-2

▲Up To Search▲

Price & Availability of IC41LV16100A-50T

	To Download IC41LV16100A-50T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .